It is well known in the art of packaging semiconductor IC chips (in modules, cards, etc.) that chips must be properly sealed within the package and appropriately heat sinked in order to achieve good thermal management. This makes it possible to dissipate the heat generated by the chips and avoid extreme temperatures that may damage the chips or, at the very least, negatively impact their reliability.
In a hermetic single or multi-chip package, the chip is attached to the substrate and is then covered with a metal or ceramic cap which is soldered around the periphery of the substrate to isolate the chip from the ambient environment. Typically, the interior of the cap is filled with a thermally conductive but electrically non-conductive paste to efficiently remove the heat from the chip and dissipate it through the package as it is generated. This allows an even flow of heat from the chip to the cap without causing any electrical shorts. The heat thus conducted to the cap is radiated into the ambient air or removed via liquid cooling.
Practitioners of the art will fully realize that meeting chip performance specifications is tightly linked to the effective and predictable operation of the thermal path from the chip to the cap, and from there to the ambient air (or cooling medium).
An essential requirement to achieve an optimum heat management is to tightly control the chip-to-cap distance. The shorter the distance the better the thermal path. Yet, if the distance is too short, there is a possibility of risking a short in addition to an uneven thermal dissipation which, in an extreme case, may even damage the chips. Furthermore, variations in the cap dimensions, chip thickness (i.e., height) and chip-to-substrate bonding, all jointly work to force greater variation from the optimum chip-to-cap distance.
It is also known in the art, that variations in chip height exist in any multi-chip package. These variations are compounded when they combine with variations in the diameter of C4 pads (controlled collapsable chip connection) which attaches a chip to the substrate. Thus, when a cap is designed, the height of the cap pedestal in combination with the stand-offs must accommodate these variations. This can result in extra space which is not required by all the chips within the package, and makes the dissipation of heat become highly inefficient.
A less desirable approach to solve this problem is to stock up caps having differing heights to accommodate the aforementioned variations. This, clearly, has the serious disadvantage of keeping a substantial quantity of multiple part numbers and procedures, which will determine which cap size is to be used and which procedure is best suited to achieve optimum thermal performance for the package under consideration. Obviously, such a solution is not practical to any manufacturing operation.